FRAMINGHAM, MA June 25, 2002 - Xelerated, the leading developer of high performance network processors and traffic managers, will demonstrate IPv6 at 10 Gbps wire-speed on an evaluation board at the Network Processor Conference East Expo in Framingham, MA tomorrow.
Xelerated's fully programmable network processors (X10s, X10d and X10q), have been designed to handle IPv6 along with any other network protocol combination, targeting vendors of metro, edge and core networking equipment. The network processors (NPUs) can easily be programmed to implement full IPv6 functionality, including multicasting, forwarding, multi-field classification for traffic conditioning, and extension header parsing - all at wire-speed.
At the exhibit in Framingham Xelerated will demonstrate IPv6, IPv4 and MPLS applications running at 10 Gbps wire-speed over SPI-4.2 ports on a FPGA. With a system clock of only 50 MHz, the FPGA contains the essential functionality of the soon-to-be-released XeleratorTM NPUs. The demo both verifies interoperability with surrounding circuitry and validates Xelerated's programmable PISCTM (Packet Instruction Set Computer) architecture.
"It's prime time for large scale IPv6 deployment, taking IPv6 from pre-deployment to carrier-grade production. New generation technology pioneers like Xelerated, with its high-class programmable network processors, is well positioned to drive this evolution," said Latif Ladid, President IPv6 Forum.
In service provider and enterprise networks deployment of IPv6 has already begun. The Gartner Group predicts that by 2006 50% of all carriers in the Asia/Pacific region will be running IPv6 in their networks.
"We have seen a growing demand for IPv6 solutions, driven by Asian customers, in particular. Our ability to do full IPv6, IPv4 and MPLS processing simultaneously at wire-speed, positions us uniquely on the market," said Thomas Eklund, Director of Business Development and founder of Xelerated.
The XeleratorTM X10 NPU family meets all the requirements imposed by IPv6, thanks to its sequential processing model and its capacity to perform very wide look-ups. This is done without compromising on the wire-speed performance inherent in the NPU. New formats for extension headers are easily accommodated since the XeleratorTM X10 NPUs do not employ hard coded packet formats. Example IPv6 application code together with IPv4 and MPLS code are included in Xelerated's development tools kit, which has been shipping to customers since January.
Xelerated will participate in a conference session on 10 Gbps network processors on Wednesday, June 26 at 8:30am in the Sheraton Framingham Hotel. In this session four vendors will discuss innovative approaches to reducing chip count and programming efforts while delivering high throughput. Representing Xelerated will be Thomas Eklund, Director of Business Development and founder of Xelerated, who is also a member of the IPv6 Forum Technical Directorate, co-author of IETF drafts and patent holder in the field of mobile Internet and IPv6.
About Xelerated
Xelerated is a fabless semiconductor company developing network processors, traffic managers and associated software for manufacturers of high-capacity networking equipment. Xelerated offers high-capacity solutions that meet the rigorous demands of established system vendors by combining the much-wanted programmability with guaranteed wire-speed performance. The XeleratorTM chip set provides for a wide range of flexible line card solutions, and ensures the smallest footprint and the lowest power consumption and chip count for the 10 Gbps market. Xelerated is located in San Jose, Boston and Stockholm. Additional information about the company and its products is available at www.xelerated.com
XeleratorTM and PISCTM are trademarks of Xelerated.