Second generation NPU sets a new standard for performance and integration for midrange enterprise and low end metro Ethernet designs.
BURLINGTON, Massachusetts, October 21, 2003 - Xelerated, developer of the XeleratorTM X10q, the industry's only 40 Gbps network processor, today announced its second generation network processor - the XeleratorTM X11. Based on the company's highly efficient data flow architecture the X11 will bring high function, low cost network processors to midrange enterprise and low end metro Ethernet designs.
The X11 is a 20 Gbps network processor that leverages the patent pending PISCTM data flow architecture introduced by Xelerated's first generation network processor, the X10q. This is the only multiprocessor architecture that offers the best of both worlds: the efficiency of a synchronous pipeline with the ease of programming of a uni-processor.
In the X11 data flow pipeline each packet passes through 360 PISCTM processors, raising the performance standard established by the X10q by 80%. Integrated 10 Gbps MACs with programmable XAUI interfaces allow direct connection to enterprise switch fabrics and Ethernet transceivers. Integrated algorithmic search co-processors allow direct connection of high performance DRAM without consuming additional processing resources. Table search bandwidth has been increased to 110 Gbps to support high functionality applications, including advanced IPv6, while using inexpensive DRAM. Xelerated will disclose the architectural details of the X11 at the Network Processor Conference in San Jose on October 23, 2003.
"Our second generation data flow processor is even more efficient than our first, allowing us to drive deeper into the Enterprise market, while maintaining full software compatibility," says Gary Lidington, VP Marketing at Xelerated.
"The availability of high performance, low cost, programmable architectures such as the X11, will facilitate graceful integration of IPv6 into the enterprise, catering for swift response to changes as networks gradually integrate IPv6 into the current IPv4-based networks," states Latif Ladid, President, IPv6 Forum and Chair European Union IPv6 Task Force.
"Xelerated has established a clear lead in cost and power with the X10q-e. The X11 should extend this lead by integrating 10 Gbps MACs with a XAUI interface," says Bob Wheeler, Sr. Analyst at The Linley Group.
"The X11 demonstrates the scalability of Xelerated's data flow architecture. Employing the same proven process technology as the X10q, the X11 provides the equivalent of 360 processors, while maintaining software compatibility and a synchronous uni-processor programming model," says John G. Metz, president of the analyst firm Metz International. "Xelerated's recent round of funding in combination with its best in class performance and strong product roadmap establishes the company as a leading start-up in the network processor space."
Availability
The XeleratorTM X11 is implemented in .13µ technology, and will sample in the third quarter of 2004
About Xelerated
Xelerated is recognized as the only network processor vendor having combined the efficiency of an ASIC with the programmability of traditional network processors. This extraordinary efficiency translates into the most cost effective solution with the highest functionality per port and lowest power consumption on the market. The company sampled its first generation of network processors in February 2003. The XeleratorTM X10q family of network processors consists of three products: the X10q-e, optimized for enterprise Ethernet and OC48 solutions; the X10q-m for advanced metro Ethernet applications; and the X10q-w for the high-end Sonet/SDH products. All products are equipped with 4 SPI4.2 ports. Xelerated has offices in Burlington, San Jose and Stockholm. Additional information is available at www.xelerated.com