Programming Model

Simplified Programming for Efficient Data Plane Software

Xelerated's approach to data plane software development focuses on efficiency and simplicity. Developing carrier-class software is really about two things: systemization of functional specification and implementation to processing hardware. Software architects should be allowed to focus on these critical tasks. In the real world, however, developers tend to be locked into an end-less iteration process of testing and rewriting of code for optimization to desirable performance.

Leveraging the deterministic design of Xelerated's Dataflow Architecture enables architects to systemize, design and implement code without the need for performance testing. This translates to significant cost savings and gains in time-to-market. Complete data plane software can be developed by two persons in just six to eight months. This contrasts to fixed-function ASIC and legacy multicore NPU programming where a team of developers would need 12 to 18 months to complete the same task.

The Dataflow Architecture is Wirespeed by Design, which cuts out the hassle of performance optimization. It takes two engineers six to eight months to develop a complete data plane, a 50% gain in time-to-market compared to competing models.

Xelerated Systemization

Layered protocols in today's public networks require management of table resources in an efficient and synchronous manner. In the systemization process, architects work out what data types should be used to store e.g. routing entries, switching policies, flow control lists, and classification and status information. A well-systemized software is the foundation for efficient use of memory bandwidth and classification resources. At Xelerated we use C data types to describe table contents, which is consistent with control plane software models.

Implementation to Dataflow Hardware

Implementing data plane software to Xelerated's Dataflow Architecture is simple. The programming model exactly mirrors the well-known sequential uni-processor model. Programmers write sequential modules avoiding the hassle of multi-parallel programming. When the software is compiled, the code is automatically mapped to the single pipeline of processor cores. One instruction takes up one processor core in the pipeline. The net effect is a model that is simple enough to allow programming in assembly language. It has been proven that amending information to protocol fields utilize operands that are all available in assembly language, and by its use, developers have full control of the processing resources.

As an instruction can include up to four operations, developers have the option to optimize resources. This frees up processor cores for additional instructions code. Resource optimization is usually an iterative process where code design, implementation and resource optimization comes together. As the architecture guarantees a defined set of instructions and lookups per packet, the process is significantly simplified in comparison to competing approaches.