Xelerated Software Development Kit
At Xelerated, we like efficient software. We want engineers developing the world’s best data plane software to have access to the right tools and to have full control of how on-chip resources and external memories are used. This is the background to Xelerated's Software Development Kit (SDK).
Programming carrier-class data plane software should focus on the right complexity. Many data plane projects grow out of time and budget due to complex code iteration to meet specific performance objectives. This is not the case when developing code for Xelerated’s chips. Focus is on systemization of resources and hardware resource optimization. And with the SDK, this is both simple and joyful. The programming model is the well-known linear single-threaded programming model. Data plane programs are written in linear sequences and the SDK builder tool maps the programs to the programmable pipeline featured in the chip. The architecture is Wirespeed by Design, and inherently guarantees a number of operations and classification actions for each packet. This cuts out performance optimization, the most painful and time consuming process associated with data plane programming.
Integrated Development Environment
The SDK comes with an Integrated Development Environment (IDE). It is project oriented and provides tight integration of all tools for programming, editing, compiling, simulating, debugging and testing the code. It supports all coding stages, from initial editing to the final stage of simulation and debugging for production ready data plane applications.
All SDK tools can be reached from the IDE. In addition, they can be accessed through a Command Line Interface.
An analyzer tool provides an overview of how the code is mapped onto the packet processing elements of the NPU, giving the programmer a good overview of how the instruction memory and classification resources are utilized.
The SDK features an Integrated Development Environment where resource utilization is easy to track.
To allow for speedy development, the programmer can define packet types and then drag-and-drop them onto the pipeline, triggering program simulation.
Simulator
The simulator enables step-by-step analysis of how defined packet types are treated by the data plane program executing along the pipeline.
The simulator provides clock cycle accurate simulation for the different chips and it also includes models for surrounding memories from Xelerated's partners to make up full line-card configurations.
It is also possible to run a control plane code and verify interaction with the data plane software using the simulator. This is useful as the programmer doesn’t need to have access to the real hardware. The software engineers can speed up the integration work of the data and control planes.
Debugger
Closely associated with the simulator is the symbolic debugger tool. The debugger is easy to use as an integral part of the IDE. With the debugger, the programmer can easily set break points, single step through the code and view code coverage.
Note! A unique feature of the Dataflow Architecture is the guaranteed performance enabling design of wirespeed systems. This literally removes the need for performance optimization. Verification of data plane software written for Xelerated’s devices boils down to verifying that the developed data plane program functions as specified. Performance is inherent.
Builder
The Xelerated builder takes the source and data type files and turns them into processor executable code, on Xelerated devices referred to as xex-files. The builder includes a complete C compatible pre-processor for usage of macros and conditional code.
Note! The Dataflow Architecture use a uniform instruction set along the complete pipeline of processor cores. The instruction set is optimized for all operations required for L2-L4 packet processing.
Key Features
Project oriented graphical IDE
Keeps all files associated with the application organized and gives intuitive access to all tools for application development.
Common environment across NPU product line
Speeds up development, encourages code co-use, and simplifies migration between use of X11, HX and AX for different target systems.
XPL Xelerated Programming Language
Easy to learn and efficient packet optimized language.
ANSI-C data structures
Allows sharing data structures with control plane, which simplifies system integration
Auto-allocation of variables to registers
High abstraction level, since the programmer does not need to deal with exact location of data during the program development.
Clock cycle accurate simulator
Shortens time-to-market by enabling early development of NPU software, and reduces need for allocating target hardware to software design
Performance guaranteed
Xelerated NPUs give deterministic packet processing performance without need for time-consuming performance optimization tools.
TCP/IP-based target hardware connection
Allows connection over the company network to e.g. a lab with target hardware for testing code remotely.
In-service debugging
Inject, capture packets and set breakpoints in live running systems without affecting other traffic. Improves system availability for the end customer.
Integrated code coverage tool
Improves quality in testing by analyzing and highlighting used/unused code and functions.
Graphical code analyzer
Overview of all used resources in the NPU and helps to optimize resource usage by visualizing how internal resources are used.
Scriptable Build Suite over CLI
Full control over the build process and integration into automated build suites.
Supported Platforms
Windows