Xelerated Software Development Kit

At Xelerated, we like efficient software. We want engineers developing the world’s best data plane software to have access to the right tools and to have full control of how on-chip resources are used. This is the background to Xelerated's Software Development Kit (SDK).

Programming carrier-class data plane software should focus on the right complexity. Many data plane projects grow out of time and budget due to complex code iteration to meet specific performance objectives. This is not the case when developing code for Xelerated’s chips. Focus is on systemization of resources and hardware resource optimization. And with the SDK, this is both simple and joyful. The programming model mirrors the well-known sequential uni-processor. Data plane programs are written in single sequences and the SDK builder tool maps the programs to the programmable pipeline featured in the chip. The architecture is Wirespeed by Design, and inherently guarantees a number of operations and classification actions for each packet. This cuts out performance optimization, the most painful and time consuming process associated with data plane programming.

Integrated Development Environment

The SDK comes with an Integrated Development Environment (IDE). It is project oriented and provides tight integration of all tools for programming, editing, compiling, simulating, debugging and testing the code. It supports all coding stages, from initial editing to the final stage of simulation and debugging for production ready data plane applications.

All SDK tools can be reached from the IDE, however they can also be accessed through a Command Line Interface.

An analyzer tool provides an overview of how the code is mapped onto the packet processing chipset, giving the programmer a good overview of how the instruction memory of pipelined processor cores are being utilized. Classification resources are also presented to the programmer.

The SDK features an Integrated Development Environment where resource utilization is easy to track.

To allow for speedy development, the programmer can define packet types and then drag-and-drop them onto the pipeline, triggering program simulation.

Simulator

The simulator enables step-by-step analysis of how defined packet types are treated by the data plane program executing along the pipeline.

The simulator provides accurate clock cycle simulation for the different chipsets and it also includes models for surrounding circuitry to make up full line-card configurations. The SDK includes models for Xelerated’s partners for e.g. memory types.

It is also possible to run the control plane code to verify interaction with the data plane software using the simulator. This is useful as the programmer doesn’t need to have access to the real chipset, and the analyzing tool helps identifying dependencies between an identified anomaly in the control plane code and data plane code.

Debugger

Closely associated with the simulator is the symbolic debugger tool. The debugger is easy to use either as an integral part of the IDE, or stand-alone using the CLI. With the debugger, the programmer can easily set break points, single step through the code and view code coverage.

Note! A unique feature of the Dataflow Architecture is the guaranteed performance enabling design of wirespeed systems. This literally removes any performance analysis. Verification of data plane software written for Xelerated’s chipsets boils down to verifying that the developed data plane program functions as specified.

Builder

The Xelerated builder takes the source and data type files and turn them into processor executable code, on Xelerated chipsets referred to as xex-files. The builder includes a complete C compatible pre-processor for usage of macros and conditional assembly.

Note! The Dataflow Architecture use a single instruction set along the complete pipeline of processor cores. The instruction set is optimized for all operations required for L2-L4 packet processing.

Key Features

IDE

Integrated graphical environment for developing, compiling, simulating and debugging carrier-class data plane software
Packet manager to define packet types. Drag-and-drop features for processing simulation of defined packet types.

Debugger and Simulator

Clock-cycle accurate simulation of programmable pipeline
Source code debugging with any text editor, e.g. CodeWright or Emacs
Code coverage
Concurrent debugging of multiple network protocols
Hardware debugging on Xelerated's network processors and programmable ethernet switches or debugging on software simulation of these devices
Debugger APIs are provided for: co-simulation of external co-processors and Look-Aside Engines; receive/transmit of data and control packets; co-simulation with the control plane

Builder

C compatible pre-processor
Translation of PISC source code to executable PISC programs
Linking of C data types
Translation of configuration program to generation of control packets for table and PISC pipeline configuration