Technology Overview

Wirespeed by Design - More Services and Higher Throughput from the Network

At the heart of Xelerated's development efforts is a patented hardware technology for programmable packet processing – the Dataflow Architecture. It was designed to empower the next wave of Carrier Ethernet infrastructure. The architecture is now offered in the third generation network processors and programmable Ethernet switches with industry leading performance and capabilities. 

The architecture is Wirespeed by Design – all packets are processed with a deterministic behavior and a guaranteed number of instructions and classification lookups per packet. The architecture handles any type of traffic, be it Ethernet, MPLS, IPv4 or IPv6. The result is a deterministic packet processing architecture which translates to unique engineering advantages:

• Scalability. Latest generation of chips scales to 100 Gbps and 150 mpps.
• Simplified programming model makes programming efficient and reduces time-to-market.
• Highest service densities and integration levels. In a single chip, the technology allows for Carrier Ethernet and IP/MPLS forwarding with off-chip access to full-Internet sized tables, metering and counting.

At Xelerated, we couple this unique architecture with adjecent key technologies. Integrated traffic management with deep off-chip packet buffers allows for new levels of cost reductions for Metro Ethernet and unified fiber access systems. By utilizing the Dataflow Architecture for OAM processing, next-generation data planes be relied upon for scalable link protection and policing of user sessions. 

The Wirespeed by Design advantages can be leveraged in a range of systems, from  low-cost over-subscribed pizza boxes for the access market to high density chassis-based systems for the service edge.

Xelerated technologies enable complete
data plane solutions for Carrier Ethernet system vendors.