Traffic Management

Wirespeed Traffic Management at High Packet Rates

When we decided to integrate a high-speed traffic manager (TM) to Xelerated’s third generation packet processing devices, we had a few main goals:

• Take the Wirespeed by Design advantages to the area of Traffic Management
• Build it solely on high volume cost-effective DRAM
• Enable custom system implementations and fully flexible configurations
• Design the TM architecture for 100 Gbps and beyond

The result is an industry leading TM hardware implementation for deterministic shaping at very high speeds. The technology complies with Broadband Forum’s TR101 and MEF10 Metro Ethernet service attributes and traffic classes. Flexible service provisioning with support for priority propagation and asymmetric traffic management makes this one of the world's most advanced integrated traffic managers.

Getting the Cost Right

Xelerated’s TM technology puts an end to the traditional trade-off between efficiency and low cost. All packets are stored in DRAM memory, which is standard in today’s market place. The Xelerated TM, however, takes this one step further. It is solely built on DRAM and there are no dependencies of SRAM.

Xelerated's Traffic Manager is equally cost-effective for small and large packet sizes. It is solely built on high volume cost-effective DRAM memory. Traffic managers using SRAM for pointer memory to packet buffers implemented in DRAM become expensive, particularly in supporting small and medium packet sizes.* 

The sole use of DRAM has two important implications. One is performance, the other cost. High-volume DRAM memory is 500 times more cost-effective than the SRAM option.

Wirespeed Performance

In alternative designs where packet pointers are stored in SRAM there is always a trade off between performance and cost. These implementations tend to trade off pointer memory for better product margins. The result is traffic management with poor performance under heavy load - which was the reason for having traffic management in the first place. 

Xelerated's TM (blue) scales pointer memory linearly to packet buffer memory. In contrast, implementations with limited pointer memory (orange) hit performance degradation for small and medium packet sizes. The orange graph illustrates a 50 Gbps TM with 2 million pointers.

Xelerated’s TM takes utilization to a new level. It enables wirespeed performance also for small packets, be it bursts of TCP acks or increasingly popular voice and video IP streaming applications. Designed for next-generation service edge systems, Xelerated's traffic manager can support over 400 ms round trip delays for any packet size.

Customize to Vendor Designs and Applications

Xelerated’s packet processing chips feature the Dataflow Architecture with a programmable pipeline of packet processing and classification resources. Drop decisions are executed by the data plane software executing in the pipeline. This program has access to traffic management hierarchical queue information, enabling vendors to implement custom active queue management algorithms. In addition, drop statistics are consistent between the TM and the pipeline for highest level of accuracy of information for billing and SLA reporting. 

Xelerated's integrated TM features queue management and hierarchical scheduling. All packet data is stored in deep buffers implemented in high volume cost-effective DRAM.

A wide range of configurations for tiered residential broadband access, enterprise SLA enforcement as well as mobile backhaul applications can be supported. The TM offers a single scheduler with scheduling nodes in a five level hierarchy.

• Nodes can be combined in a highly flexible manner for custom scheduling designs and SLA configurations.
• Efficient support for fairness and strict priority of mission-critical applications as priority levels are propagated from lower levels, e.g from user to group and port scheduling levels.
• Scheduling nodes support single or dual rate shapers and a range of scheduling algorithms: Round Robin (RR), Deficit Weighted Round Robin (DWRR) or Strict Priority Queuing (SPQ).
• An additional shaping level allows group of queues to share an extra token bucket shaper that can be used to shape the combined data rate.

Xelerated’s TM enables platforms to be designed in compliance of class of service standards. The technology is designed to ensure consistent traffic behavior for network interfacing ports as well as stacked and chassis-based configurations under normal as well as under abnormal traffic scenarios.

Scaling to 100 Gbps

Xelerated's integrated Traffic Manager supports different speeds depending on device type.

Xelerated’s traffic management technology is designed to scale beyond 100 Gbps:

• Single scheduler in control of all TM bandwidth, allowing for complete bandwidth assignment to single high capacity port.
• Scaling of buffer bandwidth linear to industry DRAM evolution.
• Linear growth of memory size. Scaling off-chip DRAM memory leads to direct increase of TM packet buffer size.
• Internal data path architectured to guarantee 100 Gbps and 150 mpps.
• TM scheduling performance independent of packet size.

Implementing integrated TM for interfaces at 100 Gbps is the biggest traffic management challenge for the next coming years. Following the industry pattern of link speed evolution, initial 100 GigE line cards will target core applications. Subsequent revisions implement full-scale traffic management for service edge applications.

Xelerated TM Advantages

*The graph illustrates memory cost for a 50 Gbps TM with 200 ms delay-bandwidth buffering. Assumptions: DRAM cost 0,002 USD/Mbit, SRAM 1 USD/Mbit and SRAM/DRAM implementation with 50% compression rate for pointer storage.